# Combinational Logic Circuit Simulation

- **Track:** Cambridge IGCSE™ Computer Science (0478 / 0984) (CAMBRIDGE IGCSE 0478)
- **Module:** Section 10: Boolean Logic & Gate Circuits
- **Estimated Duration:** 10 minutes
- **Access:** Open Theory (All-Access for Interactive IDE & Autotests)

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## Theory & Conceptual Background

Work from inputs towards the output. Label intermediate wires so you can evaluate one gate at a time.

![A and B feed AND to produce X; C feeds NOT to produce Y; X and Y feed OR to produce Q](/curriculum/igcse/logic-circuit.svg)

## Worked row

The circuit means X = A AND B, Y = NOT C, Q = X OR Y. For A=1,B=0,C=1, X=0 and Y=0, so Q=0. For A=1,B=1,C=1, X=1 and Y=0, so Q=1.

The expression is `(A AND B) OR (NOT C)`. Parentheses preserve the intended structure. To build a truth table, list all eight combinations of A,B,C and add columns for X,Y,Q. Evaluate each column in dependency order.

## Independent construction

A fan should run when Hot AND Occupied are both 1, or when Manual is 1. Draw the circuit on paper, then write its expression and complete its truth table. Keep the gates corresponding to the stated rule; do not simplify away part of the required representation.

Self-review: use one AND feeding one OR; Hot and Occupied enter AND, Manual enters the other OR input. There are three inputs and one output. Check the row Hot=0,Occupied=1,Manual=1: the output must be 1.

---

## Interactive Exercises & Autotest Specifications

### Exercise 1: Exam-Style Check: Tracing Combinational Circuit Intermediate Signals (Multiple choice, 25 XP)

**Instructions:**
A combinational logic circuit processes three binary inputs $A = 0$, $B = 1$, and $C = 1$ through three logic gates:

- Intermediate node $P = A \text{ OR } B$ (Gate 1: OR)
- Intermediate node $Q = \text{NOT }(B \text{ AND } C)$ (Gate 2: NAND)
- Final output $X = P \text{ AND } Q$ (Gate 3: AND)

What are the resulting binary values at nodes $P$, $Q$, and final output $X$?

**Options:**
- **A**: P = 1, Q = 1, X = 1
- **B**: P = 0, Q = 1, X = 0
- **C**: P = 1, Q = 0, X = 0
- **D**: P = 0, Q = 0, X = 0


**Autotest Expectations:**
- **Intermediate nodes and final output correctly evaluated**: `selection_match` -> Expected: `opt_p1_q0_x0`

### Exercise 2: Exam-Style Question: Deriving Boolean Sub-Expressions for Combinational Nodes (Fill in blank, 35 XP)

**Instructions:**
A logic circuit consists of three gates:

1. Gate 1 receives inputs $A$ and $B$ into an AND gate: $P = A \text{ [blank_1] } B$
2. Gate 2 receives input $C$ into a NOT gate: $Q = \text{[blank_2] } C$
3. Gate 3 receives signals $P$ and $Q$ into an OR gate: $X = P \text{ [blank_3] } Q$

Fill in the missing gate operator keywords (`AND`, `NOT`, `OR`).


**Starter Code:**
```text
{"template":"1. [blank_1]\n2. [blank_2]\n3. [blank_3]","word_bank":["AND","NOT","OR","NAND","NOR","XOR"],"prompt":"Exam-Style Question: Deriving Boolean Sub-Expressions for Combinational Nodes","blanks":[{"id":"blank_1"},{"id":"blank_2"},{"id":"blank_3"}]}
```

**Autotest Expectations:**
- **Gate 1 operator AND**: `text_exact` -> Expected: `AND`
- **Gate 2 operator NOT**: `text_exact` -> Expected: `NOT`
- **Gate 3 operator OR**: `text_exact` -> Expected: `OR`

### Exercise 3: Application: Circuit stages (Fill in blank, 30 XP)

**Instructions:**
Work out each answer before submitting. X = A AND B; Y = NOT C; Q = X OR Y. For A=1,B=0,C=1, X: For the same inputs, Y: For the same inputs, Q:


**Starter Code:**
```text
{"prompt":"Application: Circuit stages","template":"1. X = A AND B; Y = NOT C; Q = X OR Y. For A=1,B=0,C=1, X: [blank_1]\n2. For the same inputs, Y: [blank_2]\n3. For the same inputs, Q: [blank_3]","blanks":[{"id":"blank_1"},{"id":"blank_2"},{"id":"blank_3"}],"word_bank":["0","1"]}
```