# CPU Architecture & Von Neumann Architecture

- **Track:** Cambridge IGCSE™ Computer Science (0478 / 0984) (CAMBRIDGE IGCSE 0478)
- **Module:** Section 3: Hardware & Architecture
- **Estimated Duration:** 15 minutes
- **Access:** Open Theory (All-Access for Interactive IDE & Autotests)

---

## Theory & Conceptual Background

The **Central Processing Unit (CPU)** is the primary hardware component that executes software programs. Nearly all general-purpose microprocessors manufactured today are based on the **Von Neumann Architecture**, first proposed by mathematician and physicist John von Neumann in 1945.

---

## Learning Objectives

- Describe the **stored program concept** that underpins the Von Neumann model.
- Explain the role and function of the **ALU**, **Control Unit**, **System Clock**, and **CPU Cache**.
- Identify and describe the special-purpose **registers**: **PC**, **MAR**, **MDR**, **CIR**, and **ACC**.
- Differentiate between the three system buses: **Address Bus**, **Data Bus**, and **Control Bus**.

---

## The Stored Program Concept

Before John von Neumann, early computing machinery was hardwired to perform only one specific calculation; running a different program required physically rewiring cables and switches.

The **Von Neumann Architecture** introduced the **Stored Program Concept**:

1. **Shared Memory**: Program instructions and data are stored together in the same continuous primary memory space (**RAM**).
2. **Binary Representation**: Both instructions and data are encoded as binary numbers ($0$s and $1$s).
3. **Sequential Execution**: Instructions are fetched from memory and executed by the processor sequentially, one after another, unless a jump or branch instruction redirects execution.

---

## Core CPU Components

A modern CPU contains several interconnected hardware subsystems:

```text
+-------------------------------------------------------------------------+
|                        CENTRAL PROCESSING UNIT (CPU)                    |
|                                                                         |
|  +--------------------+   Control Signals   +------------------------+  |
|  |    Control Unit    | ------------------> | Arithmetic Logic Unit  |  |
|  |        (CU)        |                     |        (ALU)           |  |
|  +--------------------+                     +------------------------+  |
|           ^                                             ^               |
|           |                                             |               |
|  +-------------------------------------------------------------------+  |
|  |                       INTERNAL REGISTERS                          |  |
|  |     [ PC ]       [ MAR ]       [ MDR ]       [ CIR ]      [ ACC ] |  |
|  +-------------------------------------------------------------------+  |
+-------------------------------------------------------------------------+
       | Address Bus (Unidirectional)           | Data Bus (Bidirectional)
       v                                        v
+-------------------------------------------------------------------------+
|                        PRIMARY MEMORY (RAM)                             |
|          Stores Instructions and Data in Shared Memory Locations        |
+-------------------------------------------------------------------------+
```

### 1. Control Unit (CU)

- Manages and coordinates all operations of the CPU.
- Directs the flow of instructions and data through the CPU registers.
- Decodes instructions retrieved from memory.
- Generates control signals and timing pulses to synchronize ALU calculations, register transfers, and memory read/write cycles.

### 2. Arithmetic Logic Unit (ALU)

- Performs all mathematical calculations: **arithmetic operations** (addition, subtraction, multiplication, division).
- Performs all logical comparisons: **Boolean logic operations** (`AND`, `OR`, `NOT`) and relational comparisons (`<`, `>`, `==`, `!=`).

### 3. System Clock

- An electronic quartz oscillator that emits continuous electrical pulses at a fixed frequency.
- Synchronizes all internal processor operations; each micro-operation of the CPU takes a specific number of clock cycles.

### 4. Cache Memory

- Extremely fast Static RAM (**SRAM**) located directly on or adjacent to the CPU core.
- Stores frequently and recently accessed instructions and data to minimize access latency to slower dynamic RAM (DRAM).

---

## Special-Purpose CPU Registers

Registers are high-speed, temporary storage memory locations built directly inside the CPU die, operating at processor clock speed:

  
| Register | Full Name | Primary Responsibility |
| --- | --- | --- |
| **PC** | **Program Counter** | Holds the memory address of the **next instruction** to be fetched from RAM. Increments automatically after each fetch. |
| **MAR** | **Memory Address Register** | Holds the memory address of the RAM location currently being read from or written to. Directly connected to the Address Bus. |
| **MDR** | **Memory Data Register** | Holds the data word or instruction just read from RAM, or data waiting to be written out to RAM. Directly connected to the Data Bus. |
| **CIR** | **Current Instruction Register** | Holds the binary instruction that is **currently being decoded and executed** by the Control Unit. |
| **ACC** | **Accumulator** | Temporarily stores the intermediate results of arithmetic calculations and logic comparisons performed by the ALU. |

---

## System Buses

Buses are sets of parallel conductive pathways (copper tracks on the motherboard or silicon traces inside the chip) that transfer electrical signals between the CPU, memory, and input/output controllers:

### 1. Address Bus

- **Purpose**: Carries memory addresses from the CPU to RAM, specifying the physical address of the data or instruction to access.
- **Directionality**: **Unidirectional** (one-way only, from CPU $\to$ Memory).
- **Bus Width**: The number of parallel wires determines the maximum addressable memory capacity. An $n$-bit address bus can address $2^n$ distinct memory locations (e.g. a 32-bit address bus addresses $2^{32} = 4\text{ GiB}$ of RAM).

### 2. Data Bus

- **Purpose**: Carries actual data values and program instructions between the CPU, memory, and peripheral controllers.
- **Directionality**: **Bidirectional** (two-way, allowing the CPU to read data from memory and write data back to memory).
- **Bus Width**: The width of the data bus (e.g. 32-bit or 64-bit) determines the **word size**—the amount of data transferred in a single bus cycle.

### 3. Control Bus

- **Purpose**: Transmits synchronization signals, timing pulses, read/write commands, and hardware interrupt requests across CPU and peripheral components.
- **Directionality**: **Bidirectional** (signals travel both out from the CU and into the CPU from external devices).

## Written practice and self-review

The Von Neumann architecture relies on system buses to connect the Central Processing Unit (CPU) to Primary Storage (RAM).

1. State the **stored program concept** that defines the Von Neumann model.
2. Compare the **Address Bus** and the **Data Bus** in terms of:

- The type of information carried.
- The directionality of transmission (unidirectional vs bidirectional).

Write an explanation before checking the theory. Check that each claim answers the question, uses the correct concept and explains why it applies. Discuss uncertain points with a teacher. The structured exercise below checks specific facts; it does not automatically mark this explanation.

---

## Interactive Exercises & Autotest Specifications

### Exercise 1: Exam-Style Check: Von Neumann CPU Registers (Multiple choice, 25 XP)

**Instructions:**
In the Von Neumann architecture, which CPU register specifically holds the memory address of the next instruction waiting to be fetched?

**Options:**
- **A**: Memory Data Register (MDR)
- **B**: Program Counter (PC)
- **C**: Current Instruction Register (CIR)
- **D**: Accumulator (ACC)


**Autotest Expectations:**
- **Correct option selected**: `selection_match` -> Expected: `b`

### Exercise 2: Exam-Style Question: Trace Register Transfers During Fetch Stage (Fill in blank, 35 XP)

**Instructions:**
Complete the sequence of register transfers (using abbreviations PC, MAR, MDR, CIR) during the Fetch stage of the Fetch-Decode-Execute cycle:

1. The address of the next instruction is copied from the [blank_1] into the MAR.
2. The instruction located at that address in RAM is placed into the [blank_2].
3. The address in the [blank_3] is incremented by 1.
4. The instruction is copied from the MDR into the [blank_4] for decoding.


**Starter Code:**
```text
{"prompt":"Complete the sequence using register abbreviations (PC, MAR, MDR, CIR):","template":"1. Address copied to MAR from: [blank_1]\n2. Instruction fetched into: [blank_2]\n3. Register incremented by 1: [blank_3]\n4. Instruction decoded in: [blank_4]","word_bank":["PC","MDR","CIR","MAR","ACC","ALU","CU"]}
```

**Autotest Expectations:**
- **Address copied from PC**: `text_exact` -> Expected: `PC`
- **Instruction fetched into MDR**: `text_exact` -> Expected: `MDR`
- **PC is incremented**: `text_exact` -> Expected: `PC`
- **Instruction decoded in CIR**: `text_exact` -> Expected: `CIR`

### Exercise 3: Application: Check the reasoning (Fill in blank, 30 XP)

**Instructions:**
Work out each answer before submitting. Unit performing arithmetic: Unit coordinating instruction execution: Stores program instructions and data:


**Starter Code:**
```text
{"prompt":"Application: Check the reasoning","template":"1. Unit performing arithmetic: [blank_1]\n2. Unit coordinating instruction execution: [blank_2]\n3. Stores program instructions and data: [blank_3]","blanks":[{"id":"blank_1"},{"id":"blank_2"},{"id":"blank_3"}],"word_bank":["ALU","control unit","memory","registers","cache","system bus"]}
```