# The Fetch-Decode-Execute (FDE) Cycle - **Track:** Cambridge IGCSE™ Computer Science (0478 / 0984) (CAMBRIDGE IGCSE 0478) - **Module:** Section 3: Hardware & Architecture - **Estimated Duration:** 15 minutes - **Access:** Open Theory (All-Access for Interactive IDE & Autotests) --- ## Theory & Conceptual Background Every computer program consists of a sequence of binary instructions stored in primary memory. To run a program, the CPU continuously repeats a three-phase cycle called the Fetch-Decode-Execute (FDE) Cycle. Learning Objectives Trace the register-level operations of the Fetch stage step-by-step.Explain how the Control Unit carries out the Decode stage using opcodes and operands.Describe the Execute stage across arithmetic, data movement, and control instructions.Explain the role of hardware and software interrupts within the instruction cycle. Overview of the FDE Cycle +-------------------------------------------------------------+ | 1. FETCH | | - Address copied from PC to MAR | | - PC incremented by 1 (PC <- PC + 1) | | - Instruction fetched from RAM via Data Bus into MDR | | - Instruction copied from MDR to CIR | +-------------------------------------------------------------+ | v +-------------------------------------------------------------+ | 2. DECODE | | - Control Unit splits instruction in CIR into: | | * Opcode (command to execute) | | * Operand (data or memory address) | +-------------------------------------------------------------+ | v +-------------------------------------------------------------+ | 3. EXECUTE | | - CU sends control signals to CPU components (ALU/RAM) | | - Operations performed; results stored in ACC or RAM | | - Interrupt lines checked before starting next cycle | +-------------------------------------------------------------+ 1. The Fetch Stage in Detail The purpose of the Fetch stage is to retrieve the next machine-code instruction from primary memory (RAM) and bring it into the CPU. Step-by-Step Register Operations: $PC \longrightarrow MAR$: The memory address stored in the Program Counter (PC) is copied into the Memory Address Register (MAR) across the internal bus. $PC \longleftarrow PC + 1$: The Program Counter is incremented by 1 so that it points to the memory address of the next sequential instruction in memory. Memory Read Signal: The Control Unit places the address from MAR onto the Address Bus and asserts a Memory Read command on the Control Bus. $RAM \longrightarrow MDR$: The instruction located at that physical RAM address is retrieved and transferred across the Data Bus into the Memory Data Register (MDR). $MDR \longrightarrow CIR$: The instruction is copied from the MDR into the Current Instruction Register (CIR), completing the Fetch phase. 2. The Decode Stage in Detail Once the instruction is safely held in the CIR, the Control Unit (CU) decodes the binary bits to determine what action is required. Instruction Anatomy: A machine instruction is divided into two distinct logical fields: $$\text{Instruction} = \text{Opcode} + \text{Operand}$$ +---------------------------------------+---------------------------------------+ | OPCODE (6 bits) | OPERAND (10 bits) | | Specifies Operation (e.g. ADD) | Specifies Data or Address (e.g. 50) | +---------------------------------------+---------------------------------------+ Opcode (Operation Code):The binary pattern specifying the specific CPU instruction to perform (e.g., LOAD, STORE, ADD, COMPARE, JUMP).The CU consults the CPU's built-in instruction set architecture decoder.Operand:The value or address that the opcode operates on.In Immediate Addressing, the operand is the actual numerical data value (e.g. add the number 5).In Direct Addressing, the operand contains the memory address where the required data is located in RAM. 3. The Execute Stage in Detail During the Execute stage, the Control Unit directs other CPU subsystems to carry out the decoded instruction: Common Execution Scenarios: Arithmetic / Logic Calculation (e.g., ADD 200): The address 200 from the operand is loaded into the MAR.The value stored at address 200 in RAM is fetched into the MDR.The ALU adds the value in MDR to the existing value in the Accumulator (ACC).The final sum is written back into the ACC. Data Storage (e.g., STORE 350): The destination address 350 is placed into the MAR.The value currently held in the ACC is copied into the MDR.The CU asserts a Memory Write signal on the Control Bus, writing the value from MDR across the Data Bus into RAM location 350. Branch / Jump Instruction (e.g., JMP 120): The target jump address 120 in the operand is copied directly into the Program Counter (PC).The normal sequential execution ($PC + 1$) is overridden, and the next instruction will be fetched from address 120. 4. Checking for Interrupts Before the CPU begins fetching the next instruction, it checks the Interrupt Register on the Control Bus: If an external hardware event (such as a keyboard keystroke or printer out-of-paper signal) has raised an interrupt, the CPU pauses the current program, saves its registers, and executes the Interrupt Service Routine (ISR).If no interrupt is pending, the CPU begins the Fetch stage of the next instruction immediately. Written practice and self-review Once an instruction is fetched into the Current Instruction Register (CIR), the CPU proceeds through the Decode and Execute stages. Describe what occurs during the Decode stage, referencing opcode and operand.Describe what occurs during the Execute stage if the instruction requires: An arithmetic calculation (e.g. adding a value).Reading data from an additional memory address. Write an explanation before checking the theory. Check that each claim answers the question, uses the correct concept and explains why it applies. Discuss uncertain points with a teacher. The structured exercise below checks specific facts; it does not automatically mark this explanation. --- ## Interactive Exercises & Autotest Specifications ### Exercise 1: Exam-Style Check: Register Transfers in the Fetch Stage (Multiple choice, 25 XP) **Instructions:** Which sequence accurately describes the flow of data between registers during the Fetch stage of the FDE cycle? **Options:** - **A**: PC -> CIR -> ALU -> ACC - **B**: ACC -> MDR -> MAR -> PC - **C**: PC -> MAR; then RAM -> MDR -> CIR (with PC incremented) - **D**: CIR -> CU -> ALU -> MAR **Autotest Expectations:** - **Correct option selected**: `selection_match` -> Expected: `b` ### Exercise 2: Exam-Style Question: Tracing the Fetch Stage Step-by-Step (Fill in blank, 35 XP) **Instructions:** Complete the register transfer steps of the **Fetch stage**: 1. The memory address in the Program Counter (PC) is copied into the: [blank_1] 2. The Program Counter is immediately incremented by: [blank_2] 3. The instruction at that memory address in RAM is loaded across the Data Bus into the: [blank_3] 4. The instruction is copied from the MDR into the: [blank_4] **Starter Code:** ```text {"word_bank":["MAR","1","MDR","CIR","PC","ALU","ACC","2","CU"],"template":"1. Copy PC to: [blank_1]\n2. Increment PC by: [blank_2]\n3. Instruction copied from memory to: [blank_3]\n4. Instruction transferred to: [blank_4]","prompt":"Exam-Style Question: Tracing the Fetch Stage Step-by-Step","blanks":[{"id":"blank_1"},{"id":"blank_2"},{"id":"blank_3"},{"id":"blank_4"}]} ``` **Autotest Expectations:** - **Correct register sequence for the Fetch stage**: `text_exact` -> Expected: `{"blank_1":"MAR","blank_2":"1","blank_3":"MDR","blank_4":"CIR"}` ### Exercise 3: Application: Check the reasoning (Fill in blank, 30 XP) **Instructions:** Work out each answer before submitting. Register holding address of next instruction: Register holding instruction being decoded: Register holding address being accessed in memory: **Starter Code:** ```text {"prompt":"Application: Check the reasoning","template":"1. Register holding address of next instruction: [blank_1]\n2. Register holding instruction being decoded: [blank_2]\n3. Register holding address being accessed in memory: [blank_3]","blanks":[{"id":"blank_1"},{"id":"blank_2"},{"id":"blank_3"}],"word_bank":["PC","CIR","MAR","MDR","ACC","ALU","Control Unit"]} ```