CAMBRIDGE AS LEVEL 9618
Module 4
In Development
Section 4: Processor Fundamentals
CPU architecture, Von Neumann model, dedicated processor registers (PC, MAR, MDR, CIR, ACC, Status), system buses and bus width, the Fetch-Decode-Execute cycle and interrupt handling, assembly language instruction sets, and addressing modes.
6 lessons
•
90 mins total
In Development
Section 4: Processor Fundamentals is currently in development
Lessons and interactive exercises for this module are currently being prepared. Check out our complete live Cambridge IGCSE™ (0478) Track to start practicing right away!
Module Lessons
6 lessons
1
4.1 CPU Architecture & The Von Neumann Model
15 mins
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In Development
In Development
2
4.2 Processor Registers & Special Purpose Registers
15 mins
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In Development
In Development
3
4.3 System Buses & The Impact of Bus Width
15 mins
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In Development
In Development
4
4.4 The Fetch-Decode-Execute Cycle & Interrupts
15 mins
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In Development
In Development
5
4.5 Assembly Language & Instruction Sets
15 mins
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In Development
In Development
6
4.6 Addressing Modes in Assembly
15 mins
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In Development
In Development